In a DLL circuit, phases of a received clock signal CLKi (reference clock) and a signal obtained by feedback of a clock signal CLKo outputted by a variable delay circuit (voltage controlled delay line or the like) are compared by a phase comparison circuit (PD), and a comparison result is reflected in delay time of the variable delay circuit. Control is performed to advance or delay the phase of the clock signal CLKo, and an operation is performed so that finally the phases of the clock signal CLKo and the clock signal CLKi match (are locked).
In this type of DLL circuit, in a case where jitter is included in the clock signal CLKi, the jitter of the clock signal CLKi is reflected also in the clock signal CLKo. That is, since the phase comparison circuit (PD) detects phase difference due to jitter of the clock signal CLKi to perform phase adjustment, with regard to the jitter of the clock signal CLKo, phase change due to the phase adjustment is added to the jitter of the clock signal CLKi.
Accordingly, Patent Document 1 discloses a DLL circuit in which, in order to reduce the jitter of the clock signal CLKo, in a case where results of a plurality of phase comparisons all match, delay time of the variable delay circuit is adjusted based on the comparison results.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2001-290555A